Processing In Memory: PIM
Emerging techniques now allow the merging of both fast logic and dense memory on a single die. The PIM group at Notre Dame has been at the forefront of developing new architectures that utilize the resulting huge improvement in latency and bandwidth, for a wide range of applications ranging from smart memory modules to supercomputer programs such as HTMT and HPCS. Coupled with these architectures are new execution models where processing to be applied to an object is performed at the memory containing the object, rather than transporting copies all the way back to a central CPU. Likewise, multi-threading has been permeated through every aspect of a large-scale system built of PIMs, permitting huge concurrencies. A new chip called PIM Lite demonstrating these principles is about to be released for fab.
Materials to be available include posters (both real and virtual) summarizing walk-throughs of the evolution of PIM architectures at ND, demonstrations of PIM Lite running on an FPGA board, and descriptions of matching execution models, with emphasis on those most relevant to massively parallel scalable systems. Booth presentations on several of these topics are planned. Several of the key faculty members and graduate students will be in attendance.